In recent years, progress in high density circuits and the miniaturization of semiconductor devices has been made in the production of semiconductor device. A photomask (it is also called a “reticle”) is used and figures having a length shorter than exposure wavelength of an aligner used in the production of a semiconductor have been written on a wafer by the exposure of the wafer since the latter half of 1990's.
In this case, a difference between a pattern formed on a photomask and a pattern formed on a semiconductor wafer is generated by the diffraction phenomena of light. For example, patterns of design data shown in FIG. 3(a) become patterns on a wafer as shown in FIG. 3(b).
Namely, the pattern formed on a semiconductor wafer is different from the design data by the diffraction phenomena of light and so distorted.
This is called generally the optical proximity effect.
In order to change the pattern formed on a semiconductor wafer into an objective shape considering the distortion of a pattern formed on a wafer by the optical proximity effect, a photomask having a corrected pattern different from the design data is produced by adding corrections to the design data so as to change the shapes of patterns on a photomask into shapes different from the design data. The technique of forming the pattern adapted to objective design data on a wafer using the photomask having corrected patterns is called optical proximity correction (OPC).
An example of the application of the technique of optical proximity correction is shown in FIG. 9.
FIG. 9, FIG. 9(a2), FIG. 9(b2), FIG. 9(c2) and FIG. 9(d2) show the shapes of patterns in the case of patterns being formed on a wafer using pattern data shown in FIG. 9(a1), FIG. 9(b1), FIG. 9(c1) and FIG. 9(d1), respectively.
Pattern data shown in FIG. 9(a1) are design data, wherein patterns formed on a wafer corresponding to patterns 910 form patterns having either a thin width or short length because of the optical proximity effect.
FIG. 9(b1) shows data in which OPC is applied to design data (FIG. 9(a1)).
In this case, numeral 920 designates OPC patterns, wherein it is assumed that there is no defocus in the wafer exposure or the exposure of data to the wafer.
As a result, patterns formed on wafer corresponding to patterns 910 form patterns 912 shown in FIG. 9(b2) so that patterns 912 approach the shape of patterns of the objective design data as compared with patterns shown in FIG. 9(a2).
FIG. 9(c1) shows patterns of data in which OPC 920 is applied to design data 910 in the same manner as shown in FIG. 9(b1). However, when there is defocus in the wafer exposure, patterns formed on a wafer are deformed, for example, into patterns shown in FIG. 9(c2).
In the wafer exposure, considering the flatness of the wafer and the thickness of the resist, there can be a defocus of about 300 nm ordinarily.
Accordingly, an OPC technique in which supplementary patterns for increasing the defocus latitude is applied to design data is also applied as a part of the OPC technique for the purpose of the correction of shapes.
For example, as shown in FIG. 9(d1), OPC patterns 920 and supplementary patterns 930 (also called assist bars or merely OPC patterns) for increasing the defocus latitude are applied to design data 910 so that the defocus latitude can be increased.
In this case, even if there is a defocus, patterns formed on a wafer come into shapes approaching patterns of the design patterns (patterns 910 shown in FIG. 9(a1)) in the same manner as in the case of the defocus shown in FIG. 9(b2).
Namely, according to the use of OPC pattern 930 for the improvement of defocus latitude shown in FIG. 9(d1), patterns 914 formed on a wafer have the shape as shown in FIG. 9(d2), even if there is a defocus in the exposure of data to the wafer so that the deformation of the pattern caused by the diffraction of light is corrected as compared with the case shown in FIG. 9(c2). As a result, the defocus latitude is improved.
Accordingly, the improvement of the yield of products in the production of a semiconductor can be expected.
As mentioned hereinbefore, a difference between patterns in design data and shapes of patterns formed on a wafer is generated by the optical proximity effect in the process of the miniaturization of semiconductors. Therefore, in recent years, the wafer exposure simulation is employed as the effective means for the evaluation of design data, namely the evaluation of data to which OPC has been applied.
Referring to FIG. 10, a conventional method of evaluating pattern data by the wafer exposure simulation is explained.
In FIG. 10, S210 to S260 designate steps of the process.
First, the wafer exposure simulation is mentioned.
The wafer exposure simulation is done by means of device 10 provided with software for simulating shapes of patterns formed on a wafer on the basis of patterns 21 of design data as shown in FIG. 11 (the device is called a wafer exposure simulator), wherein the wafer exposure simulator is usually provided with a display and input and output terminals.
The wafer exposure simulation is ordinarily comprised of two steps of optical simulation (it is also called an optical model simulation) and resist-simulation (the resist-simulation is also called a development simulation, and one of the process model simulations). Further, there is also a case where the wafer exposure simulation is comprised of three steps of optical model simulation, resist-simulation and etching process simulation (the etching process is one of the process model simulations).
In the optical simulation, there is a condition of image formation which is determined exclusively by the wavelength of the source and number of apertures of the source (NA), and σ (σ indicates coherency and is also designated by “sigma”). Aberration and vibration of the aligner are considered selectively for optical simulation in the optical simulation.
In the resist-simulation, simulation of the development process (resist process) is carried out on the basis of the result determined exclusively by optical simulation. However, since the number of parameters is too many, calibrating test patterns and process models obtained by writing test patterns on a wafer by the exposure of data to a wafer into measuring the length of the written patterns in a simulation model is employed.
Simulation of an etching process can be carried out in the same manner as in a simulation of a development process (resist process). Therefore, the simulation of an etching process can be omitted under certain circumstances.
First, test mask 280 is formed on the basis of test pattern data 270 (S271) at S272. Then, simulation model B (designated by numeral 290 at S280) is formed through the transfer of pattern data to a wafer or the exposure of pattern data to a wafer through test mask 280 (S273) and measurement (S274) of the length of the written pattern on a wafer by the wafer exposure.
Zero defocus is ordinarily assumed for a wafer.
The wafer exposure simulation is carried out using the formed simulation model B (290) and data with OPC in which OPC is applied to design data designed for the circuit of a semiconductor device as pattern data 210 of the object of process 210, by means of the wafer exposure simulator 250, so that the shapes of patterns formed on a wafer are evaluated and proved.
Simulation model B (290 at S280) is used as a reference to pattern data 210 of the object of the process. The wafer exposure simulation is carried out at a given defocus (usually zero defocus), by which shapes of patterns formed on a wafer are evaluated.
In this case, simulation model B 290 is comprised of a group of dimension data obtained by writing patterns on a wafer by the exposure of data to the wafer through test mask 280 which is a photomask for tests produced on the basis of test pattern data 270 under the condition of the wafer exposure with a given defocus (usually zero defocus), measuring the dimensions of given transferred patterns to a wafer and relating dimension data of test pattern data 270, dimension data of test mask 280 and dimension data of patterns on the wafer at the correspondent positions with each other for the respective conditions of the wafer exposure.
Contents to be evaluated here are the evaluations of the shapes of patterns formed on a wafer. Differentials 23a, 23b between patterns 21 of data to be processed and the shapes of patterns 23 formed on a wafer on the effect of simulation are measured, as shown in block 23 of FIG. 11. In case of the differentials being larger than a prescribed value, correction is made in the step of design.
The exposure property of data to the wafer evaluated made according to conventional simulation is made using ideal design patterns and assuming that there is no error in the production of a photomask and that ideal zero defocus is set for the wafer exposure.
Therefore, errors in the production of the photomask and deformation of patterns caused by defocus in the wafer exposure could not be evaluated from the wafer exposure simulation.
Conventional methods of the evaluation of the exposure property of data to a wafer are satisfactory when the dimensions of the patterns formed on a wafer are more than about ⅔ of the exposure wavelength. However, when miniaturization progresses further, errors in the production of the photomask and deformation of the patterns caused by defocus become serious.
With high density circuits and the miniaturization of semiconductor devices progressing in recent years, in the evaluation of the exposure property of data to a wafer with conventional simulations, there was a problem that errors in the production of a photomask and deformation of patterns caused by a defocus in the exposure of data to wafer cannot be evaluated by the wafer exposure simulation because ideal design patterns are used assuming that the produced photomask has no error in the production of the photomask and that ideal zero defocus is set in the condition of the wafer exposure.
Corresponding to the above-mentioned problem, it is an object of the present invention to provide a method of evaluating the exposure property of data to a wafer in which errors in the production of a photomask and deformation of patterns caused by a defocus in the exposure of data to a wafer are considered.
Accordingly, the present invention aims at evaluating errors in the production of a photomask and the deformation of patterns cased by a defocus in the exposure of data to a wafer in the stage of design data.